//------------------------------------------------------------
//  Filename: camera_fiber_info.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2016-12-09 12:01
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps
 
module CAMERA_FIBER_INFO ( 
    input  wire         clk_100mhz,
    input  wire         resetn,

    input  wire [15:0]  camera_x_org_cnt,
    input  wire [15:0]  camera_y_org_cnt,

    input  wire [15:0]  fusion_base_x,
    input  wire [7:0]   fusion_pix_black, 
    input  wire [7:0]   fusion_face_sens,
    input  wire [7:0]   fusion_edge_sens,

    input  wire [1:0]   sensor_base, // 1 , 2 ; 0 for regs
    input  wire         sensor_wr_en,
    input  wire [32:0]  sensor_din,

    output reg  [31:0]  calibera_edge,
    output reg  [31:0]  engineer_edge,
    output reg  [31:0]  move_porc_data,
    output reg          move_porc_last,
    output reg          move_porc_v,

    input  wire [11:0]  cpu_mem_addrb,
    output reg  [31:0]  cpu_mem_doutb,
    output reg          cpu_mem_ready
); 
//-----------------------------------------------------------
localparam ENGINEER_P0 = 10; 
localparam ENGINEER_P1 = 630;
//-----------------------------------------------------------
wire        clk = clk_100mhz  ;
wire        rst = ~resetn     ;
//-----------------------------------------------------------
wire        m0_axis_tvalid  = sensor_wr_en;
wire[7:0]   m0_axis_tdata   = sensor_din[7:0];
wire        m0_axis_tlast   = sensor_din[32];
//-----------------------------------------------------------
reg[15:0]   sync_x_cnt     ;
reg[7:0]    frm_data       ;
reg         frm_last       ;
reg         frm_data_v     ;
reg         linex_sel      ;

reg[10:0]   line_mem_addr;
reg         line0_mem_ena;
reg         line0_mem_wea;
reg[7:0]    line0_mem_dina;
reg         line0_mem_enb;
reg[10:0]   line0_mem_addrb;
wire[7:0]   line0_mem_doutb;

reg         line1_mem_ena;
reg         line1_mem_wea;
reg[7:0]    line1_mem_dina;
reg         line1_mem_enb;
reg[10:0]   line1_mem_addrb;
wire[7:0]   line1_mem_doutb;

reg[10:0]   line0_mem_addra;
reg[10:0]   line1_mem_addra;
//--------------------------------------------------------
reg  [7:0]  info_mem_addra ;
reg  [7:0]  info_mem_dina  ;
reg         info_mem_wea   ;

reg  [7:0]  info_mem_addrb ;
wire [7:0]  info_mem_doutb ;

reg  [7:0]  edge_cntp_addra;
reg  [7:0]  edge_cntp_dina ;
reg         edge_cntp_wea  ;

reg  [7:0]  edge_cntp_addrb;
wire [7:0]  edge_cntp_doutb;

reg  [7:0]  edge_cntq_addra;
reg  [7:0]  edge_cntq_dina ;
reg         edge_cntq_wea  ;

reg  [7:0]  edge_cntq_addrb;
wire [7:0]  edge_cntq_doutb;

reg  [7:0]  edge_mem_addra0;
reg  [15:0] edge_mem_dina0 ;
reg         edge_mem_wea0  ;

reg  [7:0]  edge_mem_addrb0;
wire [15:0] edge_mem_doutb0;

reg  [7:0]  edge_mem_addra1;
reg  [15:0] edge_mem_dina1 ;
reg         edge_mem_wea1  ;

reg  [7:0]  edge_mem_addrb1;
wire [15:0] edge_mem_doutb1;

reg  [7:0]  edge_mem_addra2;
reg  [15:0] edge_mem_dina2 ;
reg         edge_mem_wea2  ;

reg  [7:0]  edge_mem_addrb2;
wire [15:0] edge_mem_doutb2;

reg  [7:0]  edge_mem_addra3;
reg  [15:0] edge_mem_dina3 ;
reg         edge_mem_wea3  ;

reg  [7:0]  edge_mem_addrb3;
wire [15:0] edge_mem_doutb3;
//--------------------------------------------------------
reg         frm_data_v_ff1;
reg         frm_last_ff1;
reg[10:0]   frm_data_v_ffx;
reg[10:0]   frm_last_ffx;
reg[54:0]   line_mem_addr_ffx;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        frm_data   <= 8'b0;  
        frm_last   <= 1'b0;  
        frm_data_v <= 1'b0; 
    end 
    else begin 
        frm_data   <= m0_axis_tdata;  
        frm_last   <= m0_axis_tlast;  
        frm_data_v <= m0_axis_tvalid;             
    end 
end 
//--------------------------------------------------------
always @(posedge clk ) sync_x_cnt <= camera_x_org_cnt;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        linex_sel <= 1'b0;    
    end 
    else if(frm_data_v&frm_last)begin 
        linex_sel <= 1'b0;    
    end
    else if(frm_data_v)begin 
        linex_sel <= (line_mem_addr == (sync_x_cnt - 1))?(~linex_sel):linex_sel; 
    end 
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        line_mem_addr   <= 11'b0;    
        line0_mem_dina  <= 8'b0;
        line0_mem_wea   <= 1'b0;
        line0_mem_ena   <= 1'b0;
        line1_mem_dina  <= 8'h0;
        line1_mem_wea   <= 1'b0;
        line1_mem_ena   <= 1'b0;
    end 
    else if(frm_data_v&frm_last)begin 
        line_mem_addr   <= 11'b0;    
        line0_mem_dina  <= 8'h0;
        line0_mem_wea   <= 1'b0;
        line0_mem_ena   <= 1'b0;
        line1_mem_dina  <= 8'b0;
        line1_mem_wea   <= 1'b0;
        line1_mem_ena   <= 1'b0;
    end 
    else if(frm_data_v)begin 
        line_mem_addr   <= (line_mem_addr < (sync_x_cnt - 1))? (line_mem_addr + 11'b1):'b0;   
        line0_mem_dina  <= frm_data[7:0];
        line0_mem_wea   <= (linex_sel == 1'b0)?1'b1:1'b0;
        line0_mem_ena   <= (linex_sel == 1'b0)?1'b1:1'b0;
        line1_mem_dina  <= frm_data[7:0];
        line1_mem_wea   <= (linex_sel == 1'b1)?1'b1:1'b0;
        line1_mem_ena   <= (linex_sel == 1'b1)?1'b1:1'b0;
    end
    else begin
        line0_mem_wea   <= 1'b0;
        line0_mem_ena   <= 1'b0;
        line1_mem_wea   <= 1'b0;
        line1_mem_ena   <= 1'b0;
    end
end 
always @(posedge clk) line0_mem_addra <= line_mem_addr;
always @(posedge clk) line1_mem_addra <= line_mem_addr;
//--------------------------------------------------------
always @(posedge clk) frm_data_v_ff1 <= frm_data_v;
always @(posedge clk) frm_last_ff1   <= frm_last;
//--------------------------------------------------------
always @(posedge clk) frm_data_v_ffx    <= {frm_data_v_ffx[9:0],frm_data_v_ff1};
always @(posedge clk) frm_last_ffx      <= {frm_last_ffx[9:0],frm_last_ff1};
always @(posedge clk) line_mem_addr_ffx <= {line_mem_addr_ffx[43:0],line_mem_addr};
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        line0_mem_addrb <= 11'b0;
        line1_mem_addrb <= 11'b0;
        line0_mem_enb   <= 1'b0;  
        line1_mem_enb   <= 1'b0;              
    end 
    else if(frm_data_v_ffx[4])begin 
        line0_mem_addrb <= line_mem_addr_ffx[54:44];
        line1_mem_addrb <= line_mem_addr_ffx[54:44];
        line0_mem_enb   <= 1'b1;   
        line1_mem_enb   <= 1'b1;           
    end 
    else begin
        line0_mem_enb   <= 1'b0;   
        line1_mem_enb   <= 1'b0;           
    end
end 
//--------------------------------------------------------
reg[7:0] line0_mem_doutb_ff1;
reg[7:0] line1_mem_doutb_ff1;
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        line0_mem_doutb_ff1 <= 0;
        line1_mem_doutb_ff1 <= 0;            
    end 
    else begin //line0_mem_doutb_ff1 sync with frm_data_v_ffx[7]
        line0_mem_doutb_ff1 <= line0_mem_doutb;
        line1_mem_doutb_ff1 <= line1_mem_doutb;            
    end 
end 
//--------------------------------------------------------
reg[7:0] level_line0;
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        level_line0 <= 8'b0;    
    end 
    else begin //level_line0 sync with frm_data_v_ffx[8]
        level_line0 <= line0_mem_doutb_ff1;    
    end 
end 
//--------------------------------------------------------
reg[7:0] level_line1;
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        level_line1 <= 8'b0;    
    end 
    else begin 
        level_line1 <= line1_mem_doutb_ff1;    
    end 
end
//--------------------------------------------------------
reg[7:0] pix_balck_threshold;
always @(posedge clk) pix_balck_threshold <= {1'b0,fusion_pix_black[7:1]};
//--------------------------------------------------------
wire g_level0 = (level_line0 > pix_balck_threshold)?1'b1:1'b0;
wire g_level1 = (level_line1 > pix_balck_threshold)?1'b1:1'b0;
//--------------------------------------------------------
reg[15:0] x_cntr;  //x_cntr sync with frm_data_v_ffx[10]
reg[15:0] y_cntr;
reg[7:0]  g_pix_x;
reg[15:0] g_pix_y;
reg       g_pix_v;
reg       g_burst; //g_burst sync with frm_data_v_ffx[9]
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        g_burst <= 1'b0;       
    end 
    else if (frm_data_v_ffx[9]&&(y_cntr > 2)) begin 
        if((level_line0 > (level_line1 + 5))||(level_line1 > (level_line0 + 5))) begin
            g_burst <= (g_level0 == g_level1)?1'b0:1'b1;
        end
        else begin
            g_burst <= 1'b0;       
        end
    end 
    else begin
        g_burst <= 1'b0;       
    end
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        x_cntr <= 16'h0;    
    end 
    else if(frm_last_ffx[8] == 1'b1)begin 
        x_cntr <= (sync_x_cnt - 1);    
    end 
    else if(frm_data_v_ffx[8]) begin
        x_cntr <= (x_cntr < (sync_x_cnt - 1))? (x_cntr + 16'h1):16'h0;    
    end
end 
//--------------------------------------------------------
wire new_line = (x_cntr == 0)?1'b1:1'b0;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        y_cntr <= 16'h0;    
    end 
    else if(frm_last_ffx[9] == 1'b1)begin 
        y_cntr <= 16'h0;    
    end 
    else if((x_cntr == (sync_x_cnt - 1))&&frm_data_v_ffx[10]) begin
        y_cntr <= y_cntr + 16'h1;    
    end
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        move_porc_data <= 32'b0;
        move_porc_v    <= 1'b0;
    end 
    else if(g_burst) begin 
        move_porc_data <= {x_cntr[15:0],y_cntr[15:0]};
        move_porc_v    <= 1'b1;            
    end 
    else begin
        move_porc_v    <= 1'b0;
    end
end 
//--------------------------------------------------------
reg engineer_edge0_found;
reg[15:0] engineer_edge0;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        engineer_edge0_found <= 1'b0;  
        engineer_edge0 <= 16'b0;        
    end 
    else if(move_porc_last) begin 
        engineer_edge0_found <= 1'b0; 
        engineer_edge0 <= 16'b0;     
    end
    else if((~engineer_edge0_found)&&move_porc_v&&(move_porc_data[27:16] == ENGINEER_P0)) begin 
        engineer_edge0_found <= 1'b1;
        engineer_edge0 <= move_porc_data[15:0];
    end
end   
//--------------------------------------------------------
reg engineer_edge1_found;
reg[15:0] engineer_edge1;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        engineer_edge1_found <= 1'b0;  
        engineer_edge1 <= 16'b0;        
    end 
    else if(move_porc_last) begin 
        engineer_edge1_found <= 1'b0; 
        engineer_edge1 <= 16'b0;     
    end
    else if((~engineer_edge1_found)&&move_porc_v&&(move_porc_data[27:16] == ENGINEER_P1)) begin 
        engineer_edge1_found <= 1'b1;
        engineer_edge1 <= move_porc_data[15:0];
    end
end    
//--------------------------------------------------------
reg[11:0] base_line_x;
reg[15:0] base_line_xm;
reg[15:0] base_line_xs;
reg[15:0] base_line_xt;
//--------------------------------------------------------
reg[15:0] calibera_edge0;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        calibera_edge0 <= 16'b0;        
    end 
    else if(move_porc_last) begin 
        calibera_edge0 <= 16'b0;     
    end
    else if(move_porc_v&&(move_porc_data[31:16] < base_line_x)&&(move_porc_data[31:16] > calibera_edge0)) begin 
        calibera_edge0 <= move_porc_data[31:16];
    end
end  
//--------------------------------------------------------
reg[15:0] calibera_edge1;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        calibera_edge1 <= 16'b0;        
    end 
    else if(move_porc_last) begin 
        calibera_edge1 <= {base_line_x,1'b0};     
    end
    else if(move_porc_v&&(move_porc_data[31:16] > base_line_x)&&(move_porc_data[31:16] < calibera_edge1)) begin 
        calibera_edge1 <= move_porc_data[31:16];
    end
end 
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        engineer_edge <= 32'b0;        
        calibera_edge <= 32'b0;   
    end 
    else if(move_porc_last)begin
        engineer_edge <= {engineer_edge1,engineer_edge0};  
        calibera_edge <= {calibera_edge1,calibera_edge0};     
    end 
end         
//--------------------------------------------------------
always @(posedge clk ) move_porc_last  <= frm_last_ffx[9]&(~frm_last_ffx[10]);
//--------------------------------------------------------
localparam PIX_WIDTH    = 64;
//--------------------------------------------------------
always @(posedge clk ) base_line_x  <= fusion_base_x[11:0];
always @(posedge clk ) base_line_xs <= (base_line_x - PIX_WIDTH);
always @(posedge clk ) base_line_xt <= (base_line_x + 1);
always @(posedge clk ) base_line_xm <= sync_x_cnt - PIX_WIDTH;
//-------------------------------------------------------- 
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        g_pix_x <= 8'h0;
        g_pix_y <= 16'b0;
        g_pix_v <= 1'b0;
    end 
    else if(g_burst) begin
        if(x_cntr < PIX_WIDTH) begin
            g_pix_x[7:6] <= 2'h0;
            g_pix_x[5:0] <= x_cntr;
            g_pix_v      <= 1'b1;
        end
        else if((x_cntr >= (base_line_x - PIX_WIDTH))&&(x_cntr < base_line_x)) begin
            g_pix_x[7:6] <= 2'h1;
            g_pix_x[5:0] <= x_cntr - base_line_xs;
            g_pix_v      <= 1'b1;
        end
        else if((x_cntr > base_line_x)&&(x_cntr <= (base_line_x + PIX_WIDTH))) begin
            g_pix_x[7:6] <= 2'h2;
            g_pix_x[5:0] <= x_cntr - base_line_xt;
            g_pix_v      <= 1'b1;
        end
        else if(x_cntr >= (sync_x_cnt - PIX_WIDTH)) begin
            g_pix_x[7:6] <= 2'h3;
            g_pix_x[5:0] <= x_cntr - base_line_xm;   
            g_pix_v      <= 1'b1;
        end 
        else begin
            g_pix_v      <= 1'b0;
        end
        g_pix_y <= y_cntr;
    end
    else begin
        g_pix_x <= 8'h0;
        g_pix_y <= 16'b0;
        g_pix_v <= 1'b0;
    end
end 
//--------------------------------------------------------
reg edge_info_sel;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        edge_info_sel <= 1'b0;
    end 
    else if(frm_last_ffx[9]&(~frm_last_ffx[10]))begin 
        edge_info_sel <= ~edge_info_sel;
    end 
end 
//--------------------------------------------------------
reg[8:0] edge_clr_addr;
reg[8:0] edge_clr_addr_ff1;
reg[8:0] edge_clr_addr_ff2;
reg[8:0] edge_clr_addr_ff3;
//--------------------------------------------------------
always @(posedge clk) begin
    edge_clr_addr_ff1 <= edge_clr_addr    ;
    edge_clr_addr_ff2 <= edge_clr_addr_ff1;
    edge_clr_addr_ff3 <= edge_clr_addr_ff2;    
end
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        edge_clr_addr <= 9'h0;
    end 
    else if(frm_last_ffx[9]&(~frm_last_ffx[10]))begin 
        edge_clr_addr <= 9'h0;
    end
    else begin 
        edge_clr_addr <= (edge_clr_addr[8] == 0)?(edge_clr_addr + 8'h1):edge_clr_addr;        
    end 
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        edge_cntp_addrb <= 8'b0;    
        edge_cntq_addrb <= 8'b0;    
    end 
    else if(edge_info_sel) begin 
        edge_cntp_addrb <= g_pix_x;    
        edge_cntq_addrb <= edge_clr_addr[7:0];
    end 
    else begin
        edge_cntp_addrb <= edge_clr_addr[7:0];
        edge_cntq_addrb <= g_pix_x;    
    end
end 
//--------------------------------------------------------
reg [7:0] edge_cnt;
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        edge_cnt <= 8'b0;    
    end 
    else if(edge_info_sel)begin 
        edge_cnt <= edge_cntp_doutb;    
    end 
    else begin
        edge_cnt <= edge_cntq_doutb;    
    end
end 
//--------------------------------------------------------
reg[(4*1  - 1):0] g_pix_v_ffx;
reg[(4*8  - 1):0] g_pix_x_ffx;
reg[(4*16 - 1):0] g_pix_y_ffx;
//--------------------------------------------------------
always @(posedge clk ) begin
    g_pix_v_ffx <= {g_pix_v_ffx[(3*1  - 1):0],g_pix_v};
    g_pix_x_ffx <= {g_pix_x_ffx[(3*8  - 1):0],g_pix_x};
    g_pix_y_ffx <= {g_pix_y_ffx[(3*16 - 1):0],g_pix_y};
end
//--------------------------------------------------------
wire       edge_inc_v    = g_pix_v_ffx[3        ];
wire[7:0]  edge_inc_addr = g_pix_x_ffx[3*8  +:8 ];
wire[15:0] edge_inc_info = g_pix_y_ffx[3*16 +:16];
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        edge_cntp_addra <= 8'b0;
        edge_cntp_dina  <= 8'b0;
        edge_cntp_wea   <= 1'b0;
    end 
    else if(edge_info_sel) begin 
        if(edge_inc_v) begin
            edge_cntp_addra <= edge_inc_addr;
            edge_cntp_dina  <= edge_cnt + 1;
            edge_cntp_wea   <= 1'b1;
        end  
        else begin
            edge_cntp_wea   <= 1'b0;
        end      
    end 
    else begin
        edge_cntp_addra <= edge_clr_addr_ff3[7:0];
        edge_cntp_dina  <= 8'b0;
        edge_cntp_wea   <= edge_clr_addr_ff3[8]?1'b0:1'b1;
    end
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        edge_cntq_addra <= 8'b0;
        edge_cntq_dina  <= 8'b0;
        edge_cntq_wea   <= 1'b0;
    end 
    else if(~edge_info_sel) begin 
        if(edge_inc_v) begin
            edge_cntq_addra <= edge_inc_addr;
            edge_cntq_dina  <= edge_cnt + 1;
            edge_cntq_wea   <= 1'b1;
        end  
        else begin
            edge_cntq_wea   <= 1'b0;
        end     
    end 
    else begin
        edge_cntq_addra <= edge_clr_addr_ff3[7:0];
        edge_cntq_dina  <= 8'b0;
        edge_cntq_wea   <= edge_clr_addr_ff3[8]?1'b0:1'b1;
    end
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        info_mem_addra  <= 'b0 ;
        info_mem_dina   <= 'b0 ;  
        info_mem_wea    <= 'b0 ;
    end 
    else begin 
        info_mem_addra  <= edge_clr_addr_ff3[7:0];
        info_mem_dina   <= edge_info_sel?edge_cntq_doutb:edge_cntp_doutb;  
        info_mem_wea    <= edge_clr_addr_ff3[8]?1'b0:1'b1;
    end 
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        edge_mem_wea0   <= 'b0 ;
        edge_mem_addra0 <= 'b0 ;
        edge_mem_dina0  <= 'b0 ;  

        edge_mem_wea1   <= 'b0 ;
        edge_mem_addra1 <= 'b0 ;
        edge_mem_dina1  <= 'b0 ; 

        edge_mem_wea2   <= 'b0 ;
        edge_mem_addra2 <= 'b0 ;
        edge_mem_dina2  <= 'b0 ; 

        edge_mem_wea3   <= 'b0 ;
        edge_mem_addra3 <= 'b0 ;
        edge_mem_dina3  <= 'b0 ;    
    end 
    else if(edge_inc_v) begin 
        edge_mem_wea0   <= (edge_cnt == 0)?1'b1:1'b0;
        edge_mem_addra0 <= edge_inc_addr;
        edge_mem_dina0  <= edge_inc_info;  

        edge_mem_wea1   <= (edge_cnt == 1)?1'b1:1'b0;
        edge_mem_addra1 <= edge_inc_addr;
        edge_mem_dina1  <= edge_inc_info; 

        edge_mem_wea2   <= (edge_cnt == 2)?1'b1:1'b0;
        edge_mem_addra2 <= edge_inc_addr;
        edge_mem_dina2  <= edge_inc_info; 

        edge_mem_wea3   <= (edge_cnt > 2)?1'b1:1'b0;
        edge_mem_addra3 <= edge_inc_addr;
        edge_mem_dina3  <= edge_inc_info;                
    end 
    else begin 
        edge_mem_wea0   <= 'b0 ;
        edge_mem_addra0 <= 'b0 ;
        edge_mem_dina0  <= 'b0 ;  

        edge_mem_wea1   <= 'b0 ;
        edge_mem_addra1 <= 'b0 ;
        edge_mem_dina1  <= 'b0 ; 

        edge_mem_wea2   <= 'b0 ;
        edge_mem_addra2 <= 'b0 ;
        edge_mem_dina2  <= 'b0 ; 

        edge_mem_wea3   <= 'b0 ;
        edge_mem_addra3 <= 'b0 ;
        edge_mem_dina3  <= 'b0 ;    
    end     
end 
//--------------------------------------------------------
always @(posedge clk) begin
    if(rst)begin 
        edge_mem_addrb0 <= 8'b0;
        edge_mem_addrb1 <= 8'b0;
        edge_mem_addrb2 <= 8'b0;
        edge_mem_addrb3 <= 8'b0;
        info_mem_addrb  <= 8'b0;           
    end 
    else begin
        case (cpu_mem_addrb[11:8]) 
            {sensor_base,2'h0}: edge_mem_addrb0 <= cpu_mem_addrb[7:0];
            {sensor_base,2'h1}: edge_mem_addrb1 <= cpu_mem_addrb[7:0];
            {sensor_base,2'h2}: edge_mem_addrb2 <= cpu_mem_addrb[7:0];
            {sensor_base,2'h3}: edge_mem_addrb3 <= cpu_mem_addrb[7:0];
        endcase
        info_mem_addrb  <= cpu_mem_addrb[7:0];
    end
end 
//--------------------------------------------------------
always @(*) begin
    case (cpu_mem_addrb[11:8]) 
        {sensor_base,2'h0}: cpu_mem_doutb = {8'b0,info_mem_doutb[7:0],edge_mem_doutb0[15:0]};
        {sensor_base,2'h1}: cpu_mem_doutb = {8'b0,info_mem_doutb[7:0],edge_mem_doutb1[15:0]};
        {sensor_base,2'h2}: cpu_mem_doutb = {8'b0,info_mem_doutb[7:0],edge_mem_doutb2[15:0]};
        {sensor_base,2'h3}: cpu_mem_doutb = {8'b0,info_mem_doutb[7:0],edge_mem_doutb3[15:0]};
        default:cpu_mem_doutb = 32'b0;
    endcase
end
//--------------------------------------------------------
always @(posedge clk,posedge rst) begin
    if(rst)begin 
        cpu_mem_ready <= 1'b0;        
    end 
    else begin
        cpu_mem_ready <= edge_clr_addr_ff3[8];        
    end 
end 
//--------------------------------------------------------
dp_ram_bmem DP_RAM_inst0(
    .clka  ( clk             ) ,
    .clkb  ( clk             ) ,
    .ena   ( line0_mem_ena   ) ,
    .wea   ( line0_mem_wea   ) ,
    .addra ( line0_mem_addra ) ,
    .dina  ( line0_mem_dina  ) ,
    .enb   ( line0_mem_enb   ) ,
    .addrb ( line0_mem_addrb ) ,
    .doutb ( line0_mem_doutb )
);
//--------------------------------------------------------
dp_ram_bmem DP_RAM_inst1(
    .clka  ( clk             ) ,
    .clkb  ( clk             ) ,
    .ena   ( line1_mem_ena   ) ,
    .wea   ( line1_mem_wea   ) ,
    .addra ( line1_mem_addra ) ,
    .dina  ( line1_mem_dina  ) ,
    .enb   ( line1_mem_enb   ) ,
    .addrb ( line1_mem_addrb ) ,
    .doutb ( line1_mem_doutb )
);
//--------------------------------------------------------
blk_mem_gen_8w256d  info_mem_inst0 (
    .clka  ( clk               ) ,
    .ena   ( 1'b1              ) ,
    .wea   ( info_mem_wea      ) ,
    .addra ( info_mem_addra    ) ,
    .dina  ( info_mem_dina     ) ,

    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( info_mem_addrb    ) ,    
    .doutb ( info_mem_doutb    ) 
);
//--------------------------------------------------------
blk_mem_gen_8w256d  edge_cnt_inst0 (
    .clka  ( clk               ) ,
    .ena   ( 1'b1              ) ,
    .wea   ( edge_cntp_wea     ) ,
    .addra ( edge_cntp_addra   ) ,
    .dina  ( edge_cntp_dina    ) ,

    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( edge_cntp_addrb   ) ,    
    .doutb ( edge_cntp_doutb   ) 
);
//--------------------------------------------------------
blk_mem_gen_8w256d  edge_cnt_inst1 (
    .clka  ( clk               ) ,
    .ena   ( 1'b1              ) ,
    .wea   ( edge_cntq_wea     ) ,
    .addra ( edge_cntq_addra   ) ,
    .dina  ( edge_cntq_dina    ) ,

    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( edge_cntq_addrb   ) ,    
    .doutb ( edge_cntq_doutb   ) 
);
//--------------------------------------------------------
blk_mem_gen_16w256d  edge_mem_inst0 (
    .clka  ( clk               ) ,

    .ena   ( 1'b1              ) ,
    .wea   ( edge_mem_wea0     ) ,
    .addra ( edge_mem_addra0   ) ,
    .dina  ( edge_mem_dina0    ) ,

    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( edge_mem_addrb0   ) ,    
    .doutb ( edge_mem_doutb0   ) 
);
//--------------------------------------------------------
blk_mem_gen_16w256d  edge_mem_inst1 (
    .clka  ( clk               ) ,

    .ena   ( 1'b1              ) ,
    .wea   ( edge_mem_wea1     ) ,
    .addra ( edge_mem_addra1   ) ,
    .dina  ( edge_mem_dina1    ) ,
    
    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( edge_mem_addrb1   ) ,    
    .doutb ( edge_mem_doutb1   ) 
);
//--------------------------------------------------------
blk_mem_gen_16w256d  edge_mem_inst2 (
    .clka  ( clk               ) ,

    .ena   ( 1'b1              ) ,
    .wea   ( edge_mem_wea2     ) ,
    .addra ( edge_mem_addra2   ) ,
    .dina  ( edge_mem_dina2    ) ,
    
    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( edge_mem_addrb2   ) ,   
    .doutb ( edge_mem_doutb2   ) 
);
//--------------------------------------------------------
blk_mem_gen_16w256d  edge_mem_inst3 (
    .clka  ( clk               ) ,

    .ena   ( 1'b1              ) ,
    .wea   ( edge_mem_wea3     ) ,
    .addra ( edge_mem_addra3   ) ,
    .dina  ( edge_mem_dina3    ) ,
    
    .clkb  ( clk               ) ,
    .enb   ( 1'b1              ) ,
    .addrb ( edge_mem_addrb3   ) ,   
    .doutb ( edge_mem_doutb3   ) 
);
endmodule

